1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing technologies, and more particularly to techniques effective for a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a trench gate structure and manufacturing the same.
2. Description of Related Art
Japanese Patent Laid-open Nos. 2000-196075 and 2000-277531 disclose techniques for preventing a source offset by protruding a trench gate electrode from the surface of a semiconductor substrate.
Japanese Patent Laid-open No. 2002-246596 discloses a manufacturing method of a power MISFET in which the cell pitch is reduced by a self-aligned structure. Specifically, it discloses a technique for forming a source region and a body contact region utilizing a sidewall formed on a sidewall portion of a trench gate electrode protruding from a semiconductor substrate.
Japanese Patent Laid-open No. 2005-5438 discloses a technique for turning a gate electrode surface, a source region, and a body contact region into silicide in a self-aligned manner by utilizing a sidewall formed on a side wall portion of a trench gate electrode protruding from a semiconductor substrate.
Japanese Patent No. 2647884 discloses a technique for forming an oxide film formed on the bottom portion of a trench to be thicker than the inner wall of the trench.
As an effective means of obtaining high performance in power MISFETs, shrinkage of the device structure has been advanced. However, the advancement in shrinkage of the device structure is regulated by photolithography technologies in many ways, and currently, it is difficult to achieve miniaturization of the device structure while preventing side effects.
For example, the techniques disclosed in Japanese Patent laid-open Nos. 2000-196075 and Japanese Patent Laid-open No. 2000-277531 require alignment tolerance between the gate electrode and the contact hole for connecting with the source region, and therefore, with these techniques, it is difficult to improve the cell density. The technique disclosed in Japanese Patent Laid-open No. 2002-246596 requires that the insulating film should be processed so as to be left over the gate electrode in order to insulate the gate electrode, which protrudes from the semiconductor substrate, from the source wire coupled to the source region. However, with the structure described in Japanese Patent Laid-open No. 2002-246596, there is a problem that it is impossible to form an insulating film with a stable film thickness over the gate electrode and gate withstand voltage defects become apparent. The technique described in Japanese Patent Laid-open No. 2005-5438 makes heavy use of the technique of forming patterns by a photolithography technology as the manufacturing technology. For example, the formation of the protruding portion of the gate electrode, the formation of the source region and the body contact region, and the formation of the contact hole are implemented by photolithography technology. In this case, there are a range of constraints on miniaturization of the device structure because of problems associated with alignment accuracy in the photolithography technique, so it is considered that there is a limit on miniaturization of the device structure. For this reason, a silicide process is conducted in the technique described in Japanese Patent Laid-open No. 2005-5438. However, it is difficult to advance miniaturization of the device structure to such an extent that the silicide process becomes effective. Thus, it is understood that the conventional techniques have problems in miniaturization of the device structure.
Even if it were possible to achieve the miniaturization of the device structure along the planar direction (horizontal direction) of the semiconductor substrate, there would exist side effects associated with an increase in the gate resistance because of the resulting decrease in the cross-sectional area of the trench gate electrode and with realization of shrinkage along the thickness direction (vertical direction) of the semiconductor substrate.